Single Electron Transistor Design with FTA for realizing SET-CMOS Architecture

Today’s world is in a constant state of growth. VLSI technology is no exception to the above statement. Evolution of electronics, after seeing many phases is now in the research era of single electronics. Single electron transistor (SET) is a device of the above kind. It enjoys advantages of nanometer-scale devices. But it has many constraints as far as in the action of implementation. In this paper, we discuss on the constraints and propose a fault-tolerant architecture for an efficient and robust design of system using SET. We have also designed digital logic circuits like AND, OR, NAND using NOR implementation of SET. We have also designed the digital circuits like HALF ADDER, HALF SUBTRACTOR, MUX (1:2) AND DEMUX (2:1) with NOR implementation of SET. The design significantly improves the immunity to permanent and transient faults occurring at transistor level.

Single electron Transistor (SET):

What and How?

Aggressive scaling of MOSFET dimensions to near-10-nanometer scale is expected to produce a number of fundamental reliability issues related to irregular dopant distributions, parameter fluctuations, and continuity of the channel region. These issues will need to be addressed from the design point of view in order to ensure the feasibility of classical CMOS architectures built with nanometer-scale technologies. In parallel to the scaling of conventional CMOS devices, a wide range of nano-scale quantum device architectures and related technologies are being developed for future nano-scale computation. Single electron transistors (SETs) could be among the most interesting and promising candidates for future nano-electronics because of their particular functionality and complementary characteristics with respect to CMOS.

Some preliminary results demonstrated in recent years have also shown the prospect of using silicon-based fabrication technologies for the integration of SETs with CMOS devices. While a number of successful SET logic applications have been reported by mimicking CMOS functionality, reliability-related questions such as background charge sensitivity and room temperature operation still remain among major issues to be solved for single electronics.


The structure of the typical SET consists of an isolated conductive island (single electron box) that is separated from the two external electrodes (source and drain) by tunneling junctions. The transfer of individual electrons between the electrodes and the isolated island can be controlled by the voltage that is applied to the gate electrode, based on the fundamental principle of Coulomb blockade. The dimensions of the conductive island and the tunneling junctions need to be in the order of a few nanometers to a few tens of nanometers. While larger device dimensions allow observable device operation at very low temperatures, the dimensions may need to be reduced to sub-nanometer levels in order to achieve Coulomb blockade near room temperature.

Indeed, the device is reminiscent of a typical MOSFET, but with a small conducting island embedded between two tunnel barriers, instead of the usual inversion channel. The current-voltage characteristics of the SET are as a function of different gate voltage levels. At small drain-to source voltage, there is no current since the tunneling rate is between the electrodes and the island is very low. This suppression of DC current at low voltage levels is known as the Coulomb blockade. At a certain threshold voltage, the Coulomb blockade is overcome, and for higher drain-to-source voltages, the current approaches one of its linear asymptotes.  

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  • Rajdeep Janorkar

    Single Electron Transistor Design with FTA for realizing SET-CMOS Architecture 5 months ago