Ultra SPARC Processor Architecture

Published : 01-01-2015 by : Siripurapu Naresh Kumar

Rating: 4/5 (4 votes)

UltraSPARC Architecture have RISC Characteristics.

But What is RISC ….?
Reduced Instruction Set Computing, also called “load-store architecture”
It is characterized by the standard , fixed instruction length
In the 1970's researchers noticed that a promising alternative to providing a large set of instructions to the ISA (instruction set arch.)
Simple instructions and few addressing modes
Extra stuff left out saves space for other things
Instructions conform to a simple format
Reduces decoding delays
Load-store design
Everything operates on registers only; load from memory to the large number of registers first, then manipulate the registers only; store to memory when done.

UltraSPARC is first RISC based processor announced by the Sun Micro System in 1995.

The name SPARC stands for
Scalable Processer ARChitecture

The original SPARC was developed in mid 1980.

3 major revisions to the architecture
SPARC-V7, 32bit, 1986
SPARC-V8, 32bit, 1990
SPARC-V9, 64bit, 1993

CONTENTS OF SPARC:

  • MEMORY
  • REGISTORS
  • DATA FORMATS
  • INSTRACTION FORMATS 
  • ADDRESSING MODES
  • INSTRACTION SET
  • INPUT AND OUTPUT
Memory Consists of 8-bits bytes.
All Addresses used are byte addresses.
2 bytes form a Half word.
4 bytes form a Word.
8 bytes form a Double word.

UltraSPARC programs can be written using virtual address space 2 bytes. This address space divided into Pages.

Some of pages are used by a program may be in physical memory that is sorted on Disk

Download seminar docs :

14072013080749-ultra-spark-processor-architechture.pptx