Integrated CMOS Tri-Gate Transistors

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Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single- gate or double- gate devices, but that the corner plays a fundamental role in determining the device I- V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the sub threshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

The tri-gate transistor isn’t entirely a new announcement, as the company has been talking about the technology at various events since September of 2002. Presenting at the 2006 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, Intel followed up with more details and first test results, which indicated that the tri-gate transistor, often also referred to as “3D transistor” may in fact be a technology that will make it into production one day.

The tri-gate transistor isn’t entirely a new announcement, as the company has been talking about the technology at various events since September of 2002. Presenting at the 2006 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, Intel followed up with more details and first test results, which indicated that the tri-gate transistor, often also referred to as “3D transistor” may in fact be a technology that will make it into production one day.

With the amount of transistors doubling every 18 – 24 months company is inclined more and more to reduce the transistor size which essentially lies on reducing the source, drain, gates size. Reducing the gate size created several challenges such as increasing current leakage in “off” states of a transistor – causing the overall power consumption of a semiconductor device to climb. Power consumption has been a major consideration in Chip design technology. First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50 x reductions in “off”-current when compared to regular planar transistors. All this is pretty interesting. Lets wait and see how far companies reduce the size and power consumption in future.

Tri-gate or 3-D are terms used by Intel Corporation to describe their non planar transistor architecture planned for use in future microprocessor technologies. These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electron to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. 

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